A liquid crystal display device (LCD), featured by thin thickness, light weight and low power consumption has recently come into widespread use, and is being predominantly employed as a display unit of mobile equipments, such as a portable telephone set (mobile phones or cellular phones), or a PDA (Personal Digital Assistants) or a notebook personal computer. In these days, with the progress in the technique for increasing a viewing area and for coping with moving images, the LCD display is now usable not only for mobile equipment but also for a stationary large screen display device and for a large screen size liquid crystal television set. A liquid crystal display device of an active matrix driving system is in use. As a thin type display device, a display device of the active matrix driving system employing an organic light emitting diode (OLED) also has been developed.
A typical configuration of an active matrix driving system thin type display device (one of a liquid crystal display device and an organic light-emitting diode display device) will be outlined with reference to FIG. 8. FIG. 8 is a diagram showing a configuration of essential portions of the thin type display device. Referring to FIG. 8, the active matrix driving system thin type display device includes a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970, and a data driver 980.
Unit pixels each including a pixel switch 964 and a display element 963 are arranged on the display panel 960 in the form of a matrix (for instance, 1280×3 pixel columns×1024 pixel rows in the case of a color SXGA (Super Extended Graphics Array) panel). Scan lines 961 and data lines 962 is formed. A plurality of scan lines 961, each of which sends a scan signal output from the gate driver 970 to a unit pixel, and a plurality of data lines 962, each of which sends a gray scale voltage signal output from the data driver 980 to the unit pixel are arrayed in a lattice-shaped configuration. The gate driver 970 and the data driver 980 are controlled by the display controller 950, and a clock CLK, control signals, and the like necessary for each of the gate driver 970 and the data driver 980 are supplied from the display controller 950. Video data is supplied to the data driver 980 in the form of a digital signal. The power supply circuit 940 supplies power supplies necessary for the gate driver 970 and the data driver 980, respectively. The display panel 960 is formed of a semiconductor substrate. The semiconductor substrate with thin-film transistors (Thin Film Transistors: TFTs) which are formed on an insulating substrate such as a glass substrate or a plastic substrate as pixel switches has been widely used in large-screen display devices.
Turning on (conduction)/off (non-conduction) of each pixel switch 964 in the display device is controlled by the scan signal. When the pixel switch 964 is turned on (brought into a conductive state), a gray scale voltage signal corresponding to video data is applied to the display element 963. Brightness of the display element 963 is varied according to the gray scale signal, thereby displaying an image. In the liquid crystal display device, the display element 963 includes a liquid crystal. In the organic light-emitting diode display device, the display element 963 includes an organic light-emitting diode.
Data for one screen is re-written every frame period (usually approximately 0.017 seconds, for 60 Hz driving). Data is successively selected (pixel switch 964 is turned on) every pixel row (every line) by each scan line 961. A gray scale signal is supplied to the display element 963 through the pixel switch 964 from each data line 962 during a selection period. There are cases where a plurality of pixels is simultaneously selected by scan lines or the driving is performed by a frame frequency higher than 60 Hz.
FIG. 9 is a diagram showing a typical configuration example of essential portions of the data driver 980 in FIG. 8. Referring to FIG. 9, the data driver 980 includes a shift register 801, a data register/latch 802, a set of level shift circuits 803, a reference signal generation circuit 804, a set of decoder circuits 805, and a set of output buffers 806.
The shift register 801 determines a data latch timing, based on a start pulse and the clock signal CLK. The data register/latch 802 develops input video digital data into a bit signal for each output and latches bit signals for every predetermined number of outputs based on the timing determined by the shift register 801, and outputs the bit signals to the set of level shift circuits 803 in response to an STB (strobe) signal. Each of the set of level shift circuits 803 level shifts the bit signal for each output supplied from the data register/latch 802 from a low-amplitude signal to a high-amplitude signal, and outputs complementary high-amplitude bit signals (DH, DBH) to a corresponding one of the decoder circuits 805. Each of the decoder circuits 805 selects, for each output, a reference signal corresponding to the input digital data (bit signal) from among reference signals generated by the reference signal generation circuit 804. Each of the output buffers 806 receives the reference signal selected by the corresponding one of the decoder circuits 805, and amplifies and outputs the grayscale signal corresponding to the reference signal. Output terminals of the output buffers 806 are connected to the data lines of the display device. Each of the shift register 801 and the data register/latch 802 is a logic circuit which is generally formed by low-amplitude voltage signals VE3 and VE4 (e.g., VE3=3.3V, VE4=0V) to which a corresponding supply voltage is supplied.
The set of level shift circuits 803, the set of decoder circuits 805, and the set of output buffers 806 handle high-amplitude voltage signals VE1 and VE2 (e.g., VE1=18V, VE2=0V) necessary for driving a display element, and corresponding supply voltages are supplied to the set of level shift circuits 803, the set of decoder circuits 805, and the set of output buffers 806. Level shifting from a low-amplitude voltage signal to a high-amplitude voltage signal is performed by each of the set of level shift circuits 803. The set of level shift circuits 803 include a plurality of level shift circuits corresponding to the number of bits of video digital data, each of which receives and converts the bit signal of the low-amplitude voltage signal to the bit signal of the high-amplitude voltage signal for each output.
In recent years, a demand for higher image quality has increased in mobile devices including thin type display devices for high-end applications, notebook PCs, monitors, and TVs. Specifically, there has arisen a demand for an increase in the number of colors (increase in the number of bits) (of approximately 16800 thousand colors or more) of 8-bit video digital data for each of RGB, an increase in a frame frequency (driving frequency for rewriting one screen) to 120 Hz or more for improvement of a moving image characteristic and for supporting three-dimensional display. For this reason, the data driver of a display device must process multiple-bit video digital data at high speed, and a reduction of a power supply voltage (to 0 to 2V or less, for example) of a logic circuit has been demanded.
The set of level shift circuits 803 are greatly affected by the reduced supply voltage of the logic circuit. The set of level shift circuits 803 include high-breakdown-voltage transistors each having a high breakdown voltage for a high-amplitude voltage signal. The threshold voltage of the high-breakdown-voltage transistor is comparatively high. For this reason, in case the power supply voltage of a logic circuit is lowered, and a High potential of a low-amplitude digital signal supplied to the set of level shift circuits 803 is close to the threshold voltage of the high-breakdown-voltage transistors in the set of level shift circuits 803, a drain current of each transistor which receives the low-amplitude voltage signal at a gate thereof is reduced. The drain current is proportional to a square of [(gate voltage)−(threshold voltage)]. High-speed level shifting may become thereby difficult or a level shift operation itself may be difficult to perform.
The following technique is disclosed as a technique for level shifting a low-amplitude digital signal to a high-amplitude voltage signal.
FIG. 10 is a circuit showing a configuration corresponding to the circuit disclosed in FIG. 2 of Patent Document 1 (JP Patent Kokai Publication JP-A-2-188024). Reference numerals for elements and the like in FIG. 10 are made to be different from those in FIG. 2 of Patent Document 1, for convenience of description. Referring to FIG. 10, N-channel MOS transistors M81 and M82 and P-channel MOS transistors M83 and M84 form a typical cross-coupled level shift circuit. The circuit in FIG. 10 further includes a first current supply circuit 91 and a second current supply circuit 92.
The following describes an operation of the level shift circuit (M81, M82, M83, M84). Referring to FIG. 10, voltages of a low-amplitude signal IN and a complementary signal INB of the low-amplitude signal IN assume VDD1 and VSS (in which VSS is a low-potential side supply voltage), voltages of a high-amplitude output signal OUT for the low-amplitude signal IN and a complementary signal OUTB of the high-amplitude output signal OUT assume VDD2 (in which VDD2>VDD1) and VSS.
The level shift circuit (M81, M82, M83, M84) includes:
the N-channel MOS transistors M81 and M82 which have sources connected in common to a power supply VSS, have drains connected to output terminals N74 and N73, respectively, and have gates connected to input terminals N71 and N72, respectively; and
the P-channel MOS transistors M83 and M84 which have sources connected in common to a power supply VDD2, have drains connected to the output terminals N74 and N73, respectively, and have gates cross-coupled to the output terminals N73 and N74, respectively.
The digital input signals IN and INB each having a low-amplitude (VDD1-VSS) are supplied to the input terminals N71 and N72, respectively. When the input signal IN is at a High level (=VDD1), the transistor M81 is turned on, and the output terminal N74 connected to a drain node of the transistor M81 assumes the voltage VSS. The transistor M82 is turned off, and the transistor M84 is turned on. The output terminal N73 connected to a drain node of the transistor M84 assumes a power supply voltage VDD2. On the other hand, when the input signal INB is at the High level (=VDD1), the transistor M82 is turned on, and the output terminal (OUT) N73 connected to a drain node of the transistor M82 assumes the voltage VSS. Then, the transistor M81 is turned off, and the transistor M83 is turned on. The output terminal (OUTB) N74 connected to a drain node of the transistor M83 assumes the power supply voltage VDD2.
Referring to FIG. 10, in case the amplitudes of the input signals IN and INB are reduced, at a time when potentials of the input signals IN and INB are changed, a discharging operation of the N-channel MOS transistors M81 and M82 and a charging operation of the P-channel MOS transistors M83 and M84 occur transiently at the same time. Thus, a malfunction or a short-through current between power supplies tends to occur.
Specifically, it is assumed that the input signals IN and INB are respectively set to be at a Low level (VSS) and a High level (VDD1), and that the output signals OUT and OUTB are respectively set to be at a Low level (VSS) and a High level (VDD2), as an initial state, for example. The transistors M81 and M82 are off (electrically nonconductive) and on (electrically conductive), respectively, and the transistors M83 and M84 are on and off, respectively.
When the input signals IN and INB are respectively changed to the High level and the Low level from the initial state, the transistors M81 and M82 are turned on and off, respectively, immediately after this change. Further, immediately after the change, the output signals OUT and OUTB are Low and High, respectively. The transistors M83 and M84 are on and off, respectively.
For this reason, the transistor M81 must lower a potential of the output signal OUTB to Low (VSS) with discharging capability exceeding charging capability of the transistor M83 in order to normally perform a level shift operation.
When the potential of the output signal OUTB is lowered, the transistor M84 is turned on, and the output signal OUT is raised to the power supply voltage VDD2. Then, the transistor M83 is turned off, thereby completing level shifting.
When the input signals IN and INB are respectively changed to the Low level and the High level, operations of the transistors M81 and M83 and the transistors M82 and M84 are reversed from those described above.
When the amplitude of the input signal IN is reduced, gate-to-source voltages of the N-channel MOS transistors M81 and M82 are reduced. Discharging capabilities of the N-channel MOS transistors are reduced (namely, drain currents of the transistors M81 and M82 are reduced). Then, malfunction tends to occur.
When the amplitude of the input signal IN is reduced, and when changes of the output signals OUT and OUTB are slow, even if a normal level shift operation is performed, the transistors M81 and M83 are both transiently turned on, or the transistors M82 and M84 are both transiently both turned on. Accordingly, the through current from the power supply VDD2 to the power supply VSS flows. This results in the increase in power consumption.
The first current supply circuit 91 and the second current supply circuit 92 are provided for the level shift circuit (M81, M82, M83, M84) to normally perform the level shift operation and also to achieve a high speed level shift operation, even if the amplitude of the input signal IN/INB is low in the configuration in FIG. 10.
The first current supply circuit 91 operates when the input signal IN is changed from the Low level (VSS) to the High level (VDD1). The second current supply circuit 92 operates when the input signal INB is changed from the Low level (VSS) to the High level (VDD1).
The current supply circuit 91 includes:
a P-channel MOS transistor M85 that has a source thereof connected to the power supply VDD2 and has a drain and a gate connected together;
a P-channel MOS transistor 86 that has a source connected to the power supply VDD2, has a gate connected to the gate of the P-channel MOS transistor M85, and has a drain connected to the output terminal N73;
an N-channel MOS transistor M89 that has a drain connected to the drain of the P-channel MOS transistor M85 and has a gate connected to the input terminal N71; and
an N-channel MOS transistor M90 that has a drain connected to a source of the N-channel MOS transistor M89, has a gate connected to the output terminal N74, and has a source connected to the power supply VSS.
The second current supply circuit 92 includes:
a P-channel MOS transistor M88 that has a source connected to the power supply VDD2 and has a drain and a gate connected together;
a P-channel MOS transistor M87 that has a source connected to the power supply VDD2, has a gate connected to the gate of the P-channel MOS transistor M88, and has a drain connected to the output terminal N74;
an N-channel MOS transistor M91 that has a drain connected to the drain of the P-channel MOS transistor M88 and has a gate connected to the input terminal N72; and
an N-channel MOS transistor M92 that has a drain connected to a source of the N-channel MOS transistor M91, has a gate connected to the output terminal N73, and has a source connected to the power supply VSS.
It is assumed that the input signals IN and INB are respectively set to be at a Low level (VSS) and at a High level (VDD1), and that the output signals OUT and OUTB are respectively set to be at a Low level (VSS) and a High level (VDD2), as the initial state. The transistors M81 and M82 are off and on, respectively, and the transistors M83 and M84 are on and off, respectively. A description will be directed to a case where the input signal IN and INB are respectively changed to the High level (VDD1) and the Low level (VSS) from this initial state.
Immediately after the input signal IN and the input signal INB have been respectively changed to the High level (VDD1) and the Low level (VSS), the transistors M81 and M82 are respectively turned on and off. Immediately after the input signal IN and the input signal INB have been respectively changed to the High level (VDD1) and the Low level (VSS), the output signal OUT is Low and the output signal OUTB is High. The transistors M83 and M84 are respectively on and off.
In the first current supply circuit 91, the input signal IN at the High level (VDD1) is supplied to the gate of the transistor M89, and the output signal OUTB at the High level (VDD2) is supplied to the gate of the transistor M90, so that the transistors M89 and M90 are both turned on. Then, a drain current responsive to a voltage between a gate voltage (VDD1) and a source voltage (VSS) of the transistor M89 is supplied to the transistor M85 of a current mirror (M85, M86). An output current (mirror current) obtained by folding back an input current to the current mirror is output from the drain of the transistor M86 to charge the output terminal N73. A drain current (mirror current) of the transistor M86 is set to a current obtained by amplifying the input current to the current mirror. The drain current of the transistor M86 raises a potential of the output signal OUT at the output terminal 73 and turns off the transistor M83. An amplification factor (mirror ratio) of the output current to the input current of the current mirror is determined by a gate width ratio of the transistor M86 to the transistor M85, (which is larger than one), when gate lengths of the transistors M85 and M86 are set to be the same.
On the other hand, the transistor M81 is turned on to reduce the potential of the output signal OUTB at the output terminal N74 to which the drain of the transistor M81 is connected. The transistor M84 is thereby turned on, and level shifting is completed.
When the potential of the output signal OUTB is lowered, the transistor M90 at the first current supply circuit 91 is turned off. The first current supply circuit 91 is thereby stopped. As described above, the first current supply circuit 91 quickly raises the potential of the output terminal N73 immediately after the change from the initial state, thereby turning off the transistor M83. For this reason, the transistor M81 can quickly lower the potential of the output signal OUTB at the output terminal N74. Accordingly, the level shift operation can be normally performed at high speed.
The second current supply circuit 92 operates when the input signal INB is changed from the Low level to the High level. It is assumed that the input signals IN and INB are respectively set to be at the High level (VDD1) and the Low level (VSS), and that the output signals OUT and OUTB are respectively set to be at the High level (VDD2) and the Low level (VSS), as the initial state.
The transistors M82 and M81 are respectively off and on, and the transistors M84 and M83 are respectively on and off. A description will be directed to a case where the input signals IN and INB are respectively changed to the Low level (VSS), and the High level (VDD1).
Immediately after the input signals IN and INB have been respectively changed to the Low level (VSS) and the High level (VDD1), the transistors M81 and M82 are respectively turned off and on. Immediately after the input signals IN and INB have been respectively changed to the Low level (VSS) and the High level (VDD1), the output signals OUT and OUTB are respectively High and Low. The transistors M83 and M84 are respectively off and on.
In the second current supply circuit 92, the input signal INB at the High level (VDD1) is supplied to the gate of the transistor M91, and the output signal OUT at the High level (VDD2) is supplied to the gate of the transistor M92, so that the transistors M91 and M92 are both turned on. Then, a drain current responsive to a voltage between a gate voltage (VDD1) and a source voltage (VSS) of the transistor M91 is supplied to the transistor M88 of a current mirror (M88, M87). An output current (mirror current) obtained by folding back an input current to the current mirror is output from the drain of the transistor M87 to charge the output terminal N74. A drain current (mirror current) of the transistor M87 is set to a current obtained by amplifying the input current to the current mirror. The drain current of the transistor M87 raises the potential of the output signal OUTB at the output terminal 74 and turns off the transistor M84. An amplification factor (mirror ratio) of the output current to the input current of the current mirror is determined by a gate width ratio of the transistor M87 to the transistor M88, (which is larger than one), when gate lengths of the transistors M88 and M87 are set to be the same.
On the other hand, the transistor M82 is turned on, and the potential of the output signal OUTB at the output terminal N74 to which the drain of the transistor M82 is connected is lowered to the power supply voltage VSS. As a result, the transistor M84 is turned on, and the output signal OUT is raised to the power supply voltage VDD2. Level shifting is thereby completed.
When the potential of the output signal OUT is lowered, the transistor M92 of the second current supply circuit 92 is turned off, so that the second current supply circuit 92 is stopped. As described above, in the second current supply circuit 92, the potential of the output terminal N74 is quickly raised to turn off the transistor M84. The transistor M82 can therefore quickly reduce the potential of the output signal OUT of the output terminal N73. Accordingly, the level shift operation can be normally performed at high speed.
As described above, the level shift circuit in FIG. 10 can perform level shifting to a high-amplitude output signal even when the amplitude of an input signal is low.
Further, the output signals OUT and OUTB are changed quickly in the circuit in FIG. 10. Accordingly, a period of time during which the transistors M81 and M83 are transiently and simultaneously turned on or a period of time during which the transistors M82 and M84 are transiently and simultaneously turned on is short. The through current can be thereby suppressed.
Patent Document 2 (JP Patent Kokai Publication No. JP-P-2003-115758A) discloses a technique performing level shifting of a video digital signal with a low amplitude (0V to 3V) to a voltage signal with a high amplitude (0V to 10V) for driving a display element in a data line driving circuit for liquid crystal driving, formed of poly silicon thin film transistors. FIG. 11 is a diagram cited from FIG. 1 in Patent Document 2. Referring to FIG. 11, a level shift circuit includes an N-channel MOS transistor MN1 connected between a terminal N62 and an input terminal N61 to which a low-amplitude input signal IN is supplied, an N-channel MOS transistor MN2 that has a source connected to the GND and has a gate connected to the terminal N62, an N-channel MOS transistor MN3 that has a source connected to a drain of the transistor MN2 and has a drain connected to a terminal N63, a P-channel MOS transistor MP1 that has a source connected to a 10V power supply and has a drain connected to the terminal N63, and an inverter (MN4, MP2) connected between the terminal N63 and an output terminal N64. A signal XSMP is supplied to a gate of the N-channel MOS transistor MN1. The inverter operates between the 10V power supply and the GND. Capacitances C1 and C2 capable of temporarily holding terminal voltages are connected to the terminals N62 and N63, respectively. A signal SMP is supplied in common to gates of the transistors MN3 and MP1. Each of the signals SMP and XSMP is a sampling control signal with a high amplitude (0V to 10V). The signal XSMP is a complementary signal of the signal SMP. FIG. 11 shows a sampling level converting unit of the data line driving circuit. Low-amplitude video serial data is supplied to the input terminal N61. When the sampling control signal SMP is Low (0V) and the signal XSMP is High (10V), the transistor MN1 is turned on to sample the serial data supplied to the input terminal N61. A low-amplitude data signal at a High (3V) level or a Low (0V) level is then held in the capacitance C1 connected to the terminal N62. In this case, the transistors MP1 and MN3 are respectively turned on and off. The terminal N63 is precharged to High (10V), and a signal OUT of the output terminal N64 is set to Low (0V) by the inverter (MN4, MP2).
Next, when the sampling control signal SMP is changed to High (10V) and the signal XSMP is changed to Low (0V), the transistor MN1 is turned off, and the data signal held in the capacitance C1 connected to the terminal N62 is continuously held. The transistors MP1 and MN3 are respectively turned off and on. Since the transistor MN3 is turned on, a voltage at the terminal N63 is changed according to the data signal held in the capacitance C1 connected to the terminal N62. That is, when the data signal for the terminal N62 is High (3V), the transistor MN2 is turned on. The voltage at the terminal N63 is then changed to Low (0V) from High (10V) to be held in the capacitance C2. When the data signal for the terminal N62 is Low (0V), the transistor MN2 is turned off, and the voltage at the terminal N63, which remains High (10V), is held in the capacitance C2. On the other hand, a voltage at the output terminal N64 is an inverter output of an output at the terminal 63. The voltage at the output terminal N64 therefore has a logical value opposite to a logical value of the terminal N63. That is, a high-amplitude data signal having a same logical value as the low-amplitude data signal at the terminal N62 is output from the output terminal N64. In the configuration in Patent Document 2, a high-voltage latch circuit (not shown) is connected to a stage subsequent to the output terminal N64 in FIG. 11, and a level-shifted voltage signal is stably held in the latch circuit for a predetermined period of time, and the latched signal is supplied to a decoder (DAC) (in FIG. 22 of JP Patent Kokai Publication JP-P-2003-115758).    Patent Document 1: JP Patent Kokai Publication No. JP-A-2-188024    Patent Document 2: JP Patent Kokai Publication No. JP-P2003-115758A